Semiconductor wafer, semiconductor chip, semiconductor device and method for manufacturing semiconductor device

ABSTRACT

There is provided an electrical characteristic test technique for a semiconductor device that can shorten the time required for a next probe test after a wafer level burn-in test, prevent leak of defective product to an assembling process and moreover easily realizes the analysis of cause for generation of a fault after delivery of products to customers. In this electrical characteristic test technique, a multi-chip package MCP mounts a couple of semiconductor chips of flash memory and SRAM, a simultaneous contact check is executed for an input/output pad of each semiconductor chip and an erase/write mode and a read mode are respectively executed for a memory array of each semiconductor chip depending on the steps S 201  to S 211  on the occasion of conducting the wafer level burn-in of the semiconductor chip of flash memory, historical data of these test results is written into the semiconductor chip of flash memory and the historical data written in the wafer level burn-in process is read in a next probe test process and the probe test is continuously implemented only to the semiconductor chip of a good product.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an electrical characteristictest technique for a semiconductor device and particularly to thetechnique that can be effectively adapted to the method of storinghistorical information of the burn-in test under the semiconductor wafercondition, so-called the wafer level burn-in a semiconductor device suchas MCP (Multi-Chip Package) mounting a couple of semiconductor chips,for example, a flash memory and SRAM.

[0002] Following techniques have been proposed for the semiconductordevice burn-in test as the technique which the inventors of the presentinvention have investigated. For example, the burn-in process of MCPmounting a flash memory and SRAM is generally conducted in the mannerthat the temperature and voltage stress exceeding the rating are appliedin the testing process in which the semiconductor chips of the flashmemory and SRAM are mounted on a substrate and these are electricallyconnected with the wire bonding method and are then molded with a resinto assemble the package structure. With this burn-in process, MCP havingprobability of a future fault is screened and only the good MCP is goodMCP is delivered as a product.

[0003] As the technique for the pretest before the wafer test such asthe burn-in test as explained above and the technique to store the wafertest result into a memory array, there are provided, for example, thetechniques described in Japanese Unexamined Patent Publication Nos. HEI8(1996)-23016 and HEI 6(1994)-5098. The technique described in theJapanese Unexamined Patent Publication No. HEI 8(1996)-23016 is proposedto store the information about good or defective products of the pretestinto the redundant area of memory or to the particular area of thenormal memory in order to reduce the next wafer test time. The techniquedescribed in the Japanese Unexamined Patent Publication No. HEI 6-5098proposes the write operation of electrical characteristic during thewafer test to the redundant memory.

SUMMARY OF THE INVENTION

[0004] Here, investigation by the inventors of the present invention forthe MCP burn-in technique explained above has made apparent that sincethe yield of the semiconductor chips of the flash memory and SRAM giveslarge influence on the yield of MCP after the assembling and thereforeit is difficult to expect the improvement in the yield of MCP in themethod of burn-in after the assembling of MCP as explained above.Namely, when this method is employed, if a fault is generated in any oneof the semiconductor chips of flash memory and SRAM, the MCP assembledusing these elements also becomes a fault and therefore it is thoughtthat the yield of assembled element is deteriorated.

[0005] Therefore, the inventors of the present invention have found amethod to redundantly relieve or reject semiconductor chips of defectiveproducts before the assembling by conducting the wafer level burn-inunder the semiconductor wafer condition in order to improve the yield ofthe semiconductor chips of the flash memory and SRAM. In this case, forexample, like the assembled products, each probe connected to thetesting apparatus is placed in contact with each terminal of thesemiconductor chip, electrical conductivity is checked between eachprobe in the contact condition and each terminal and thereafter thescreening can be realized by executing the erase/write mode and the readmode.

[0006] However, in such wafer level burn-in, it is probable that aproblem of time is generated and defective product is leaked to theassembling process because the probe test is executed to all chipsincluding the chip found as a defective product in the burn-in testafter such a wafer level burn-in test is completed. Moreover, it is alsothough as a problem that analysis for the cause of fault when a fault isgenerated in the product after the assembled products are delivered tocustomers.

[0007] In the techniques described in the Japanese Unexamined PatentPublication Nos. HEI 8(1996)-23016 and HEI 6(1994)-5098, the result ofpretest before the wafer test and the result of the wafer test arestored in the memory array and these techniques are different from thetechnique for storing the historical data of the wafer level burn-inwhich is conducted in the semiconductor wafer condition just like thepresent invention.

[0008] It is therefore an object of the present invention to provide anelectrical characteristic testing technique of a semiconductor devicethat can reduce the probe testing time, prevent leakage of defectiveproducts into an assembling process and moreover easily realize analysisof cause of generation of defective products after the delivery tocustomers by storing the historical data of this wafer level burn-inwhile the wafer level burn-in process is introduced.

[0009] The abovementioned and the other objects and novel features ofthe present invention will become more apparent from the description ofthe present specification and the accompanying drawings.

[0010] Typical inventions among those disclosed in the presentspecification can be briefly summarized as follows.

[0011] (1) A semiconductor wafer of the present invention mounts aplurality of semiconductor chips each of which also includes anon-volatile memory array, wherein said semiconductor chip comprises afirst memory area for storing input information of usual operation and asecond memory area for storing historical information of an electricalcharacteristic test of the first memory area. Moreover, in thissemiconductor wafer, the electrical characteristic test is also adaptedto the wafer level burn-in test. In addition, the second memory area maybe adapted to the flash fuse area and OTP area or the lock bit area ofthe non-volatile memory area. Otherwise, the second memory area can beadapted to a part of the first memory area of the non-volatile memoryarea.

[0012] (2) The semiconductor chip of the present invention has anon-volatile memory array including a first memory area for storing aninput information of usual operation and a second memory area forstoring the historical information of the electrical characteristic testof the first memory area. Moreover, in the semiconductor chip, theelectrical characteristic test is adapted to the wafer level burn-intest.

[0013] (3) The semiconductor device of the present invention mounts asemiconductor chip comprising a first memory area for storing inputinformation of usual operation and a second memory area for storinghistorical information of an electrical characteristic test of the firstmemory area. Moreover, in the semiconductor device explained above, theelectrical characteristic test can be adapted to the wafer level burn-intest.

[0014] (4) The other semiconductor device of the present inventionmounts a first semiconductor chip including a non-volatile memory arraycomprising a first memory area for storing input information of usualoperation and a second memory area for storing historical information ofan electrical characteristic test of the first memory area and a secondsemiconductor chip including a non-volatile memory array comprising athird memory area for storing an input information of usual operation,thereby for storing historical information of an electricalcharacteristic test of the third memory area of the second semiconductorchip in the second memory area of the first semiconductor chip.Moreover, the electrical characteristic test is adapted to the waferlevel burn-in test in the other semiconductor device explained above.

[0015] (5) A method of manufacturing a semiconductor device of thepresent invention is adapted to a semiconductor device mounting asemiconductor chip having a nonvolatile memory array cut out from asemiconductor wafer, comprising a process to conduct an electricalcharacteristic test of a first memory area for storing input informationof usual operation of the semiconductor chip before cutting out thesemiconductor chip from the semiconductor wafer and a process to storehistorical information of the electrical characteristic test to thesecond memory area of the semiconductor chip. Moreover, the electricalcharacteristic test in the method of manufacturing a semiconductordevice may be adapted to the wafer level burn-in test. In addition, onthe occasion of conducting the wafer level burn-in test, the historicalinformation of the second memory area is temporarily saved to a testingapparatus before the wafer level burn-in test and the historicalinformation after the wafer level burn-in test is combined with thatbefore the burn-in test to store the combined information into thesecond memory area.

[0016] (6) A method of manufacturing the other semiconductor device ofthe present invention relates to a method of manufacturing asemiconductor device mounting a first semiconductor chip having anon-volatile memory array cut out from a semiconductor wafer and asecond semiconductor chip having a volatile memory array, comprising thesteps of: conducting an electrical characteristic test of the firstmemory area for storing input information of usual operation of thefirst semiconductor chip before cutting out the semiconductor chip fromthe semiconductor wafer; storing historical information of an electriccharacteristic test of the first memory area of the first semiconductorchip to the second memory area of the first semiconductor chip;conducting an electrical characteristic test of the third memory areafor storing input information of usual operation of the secondsemiconductor chip before cutting out the semiconductor chip from thesemiconductor wafer; and storing the historical information of anelectrical characteristic test of the third memory area of the secondsemiconductor chip to the second memory area of the first semiconductorchip. Moreover, in the method of manufacturing the semiconductor device,the electrical characteristic test is adapted to the wafer level burn-intest. In addition, on the occasion of conducting the wafer level burn-intest, the historical information of the second memory area of the firstsemiconductor chip is temporarily saved to a testing apparatus beforethis burn-in test, and the historical information is combined, afterthis burn-in test, with that before the burn-in test and this combinedhistorical information is stored in the second memory area of the firstsemiconductor chip.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a cross-sectional view showing a semiconductor device asa preferred embodiment of the present invention.

[0018]FIG. 2 is a block diagram showing a semiconductor chip of theflash memory in the preferred embodiment of the present invention.

[0019]FIG. 3 is a layout showing the semiconductor chip of the flashmemory in the preferred embodiment of the present invention.

[0020]FIG. 4 is a flowchart showing a method of manufacture up to theassembling process from the wafer process of the semiconductor device inthe preferred embodiment of the present invention.

[0021]FIG. 5 is a plan view showing the semiconductor wafer condition inthe preferred embodiment of the present invention.

[0022]FIG. 6 is a plan view showing the semiconductor chip condition inthe preferred embodiment of the present invention.

[0023]FIG. 7 is a block diagram showing a test system to realize thewafer level burn-in test in the preferred embodiment of the presentinvention.

[0024]FIG. 8 is a flowchart showing the wafer level burn-in test of theflash memory in the preferred embodiment of the present invention.

[0025]FIG. 9 is a block diagram showing a circuit including the waferlevel burn-in function of the flash memory in the preferred embodimentof the present invention.

[0026]FIG. 10 is a timing chart showing the wafer level burn-in mode inthe preferred embodiment of the present invention.

[0027]FIG. 11 is an explanatory diagram showing a data format in thewafer level burn-in mode in the preferred embodiment of the presentinvention.

[0028]FIG. 12 is an explanatory diagram showing a setup command in thewafer level burn-in mode in the preferred embodiment of the presentinvention.

[0029]FIG. 13 is a structural diagram showing a detail of the memoryarray in the preferred embodiment of the present invention.

[0030]FIG. 14 is an explanatory diagram showing a relationship among theusual memory area, redundant memory area, OTP area, erase operation,write operation and read operation for the flash fuse area in thepreferred embodiment of the present invention.

[0031]FIG. 15 is an explanatory diagram showing a relationship among theusual memory area, redundant memory area, OTP area, implementation ofburn-in test for the flash fuse area and storing area of burn-in testresult assumed as the historical data of the electrical characteristictest.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0032] The preferred embodiment of the present invention will beexplained in detail with reference to the accompanying drawings thereof.

[0033] First, a structure of an example of the semiconductor device ofthe preferred embodiment will be explained with reference to FIG. 1.FIG. 1 is a cross-sectional view showing a semiconductor device.

[0034] The semiconductor device of this embodiment is defined as an MCP(Multi-Chip Package) mounting a couple of semiconductor chips of a flashmemory, for example, as electrically programmable and erasablenon-volatile memory and SRAM (Static type Random Access Memory) and iscomposed of a substrate 1, a semiconductor chip 2 of flash memory as anon-volatile memory mounted on this substrate 1, a semiconductor chip 3of RAM as a non-volatile memory mounted on the semiconductor chip 2 ofthis flash memory, a wire 4 connecting the terminals of thesemiconductor chips 2, 3 and terminals on the substrate 1, a solder ball5 electrically connected to the terminals on the substrate 1 via thewiring pattern and through hole to become an external terminal arrangedon the rear surface of this substrate 1 and a resin 6 for molding thesemiconductor chips 2, 3 and wire 4. This MCP is not restricted only tosuch structure and is also not restricted to the mounting of the flashmemory and SRAM.

[0035] The substrate 1 is composed, for example, of a resin substrate ofthe multi-layer structure, a ceramic substrate or a tape substrate,wherein a metal pad as an electrode terminal formed, for example, ofgold (Au) is provided on the front surface, a metal land as an electrodeterminal formed of Au or the like is provided on the rear surface andthe metal pad on the front surface is electrically connected with themetal land at the rear surface via the through hole among respectivelayers and the wiring pattern of each layer.

[0036] The semiconductor chip 2 of flash memory is provided with themetal pad formed of Au or the like at the front surface and also formstherein the predetermined integrated circuit such as a non-volatileEEPROM (Electrically Erasable and Programmable Read Only Memory) andeach terminal of the integrated circuit within this chip is electricallyconnected up to the metal pad on the front surface of chip. Thesemiconductor chip 2 of this flash memory is mounted on the frontsurface of substrate 1 at the rear surface side thereof and the metalpad on the semiconductor chip 2 is electrically connected to the metalpad on the front surface of the substrate 1 with the wire 4.

[0037] The semiconductor chip 3 of SRAM is provided, at the surfacethereof, with a metal pad formed of Au and forms therein thepredetermined integrated circuit of volatile SRAM. Each terminal of theinternal integrated circuit is electrically connected up to the metalpad at the surface. The rear surface side of the semiconductor chip 3 ofthis SRAM is mounted on the surface of the semiconductor chip 2 of flashmemory and the metal pad on the surface of semiconductor chip 3 iselectrically connected to the metal pad on the surface of substrate 1with the wire 4.

[0038] The wire 4 is formed, for example, of a metal wire of Au and thiswire 4 electrically connects the metal pad at the surface of thesemiconductor chips 2, 3 and the metal pad at the surface of thesubstrate 1.

[0039] The solder ball 5 is formed as a ball, for example, of lead(Pb)/Sn (Tin) or a metal material not including lead. This solder ball 5is joined with the metal land on the rear surface of the substrate 1 andis arranged, for example, in the form of an array on the rear surface ofthe substrate 1.

[0040] The resin 6 is composed, for example, of an epoxy-based resinmaterial having insulation property and this resin 6 seals the surfaceof substrate 1 covering the semiconductor chips 2, 3 and wire 4.

[0041] The MCP structured as explained above electrically connects up tothe solder ball 5 joined with the metal land of this substrate 1 fromeach terminal of the semiconductor chip 2 of flash memory and theintegrated circuit of the semiconductor chip 3 of SRAM via the metal padand wire 4 on the surfaces of the semiconductor chips 2, 3, metal pad onthe surface of substrate 1, through hole of each layer, wiring patternof each layer and metal land on the rear surface of the substrate 1.

[0042] Next, with reference to FIG. 13 and FIG. 14, an example ofstructure of a semiconductor chip of the flash memory will be explainedbased on the FIG. 2. FIG. 2 is a block diagram showing the semiconductorchip of the flash memory, while FIG. 13 is structural diagram showingthe detail of the memory array and FIG. 14 is an explanatory diagramshowing relationship among the erase operation, write operation and readoperation to the memory cell area.

[0043] The semiconductor chip 2 of flash memory is composed of a memoryarray MA in which a plurality of memory cells are arranged like alattice, X-system X-address buffer XAB and X-decoder XD for selectingthe desired memory cells within this memory array MA, Y-axis Y-addressbuffer YAB and Y-decoder YD, a Y-switch/sense amplifier YS/SA forinputting and outputting data for the selected memory cells, amultiplexer MP, an input/output buffer IOB, a command user interface CUTfor generating the sequence of erase/write, read mode, a write statemachine WSM and a data handler DH or the like. As shown in the figure,the memory array MA includes an ordinary memory cell area NMR, a flashfuse area FFA, an OTP area OTPA, a lock bit area LBA, an X-redundantmemory cell area XRA and a Y-redundant memory cell area YRA. The areasFFA, OTPA, LBA, XRA and YRA can be selected with the commands formedthrough combination of the predetermined signals to be inputted to acommand user interface CUT. This CUT sets selectively only one signalamong the selection signals S1 to S5 to the enable state to uniquelyselect the areas FFA, OTPA, LBA, XRA and YRA.

[0044] In this semiconductor chip 2 of the flash memory, the addresssignals A7 to A20 are inputted to the X-address buffer XAB as theexternal address signal and the address signals A0 to A6 to theY-address buffer YAB, respectively. Moreover, as the control signals, achip enable signal/CE, an output enable signal/OE, a write enablesignal/WE and a write protect signal/WP, a reset/power-down signal/RPare respectively inputted to the command user interface CUI and aready/busy signal RDY//BUSY is outputted from the write state machineWSM. Moreover, the input/output data I/O0 to I/O15 are inputted andoutputted via the input/output buffer IOB. In addition, the power supplyvoltage VCC and reference voltage VSS are also supplied from theexternal circuits.

[0045] As the basic operations of the semiconductor chip 2 of the flashmemory, the X-direction address within the memory cell area NMR of thememory array MA is designated with the X-address buffer XAB andX-decoder XD based on the externally inputted address signals A7 to A20,while the Y-direction address is designated with the Y-address bufferYAB and Y-decoder YD based on the address signals A0 to A6, in order toselect the memory cells allocated at the intersecting points of the wordline and bit line based on the designated addresses. With theerase/write operations for these selected memory cells, the input/outputdata I/O0 to I/O15 are inputted to the memory cells as the erase/writedata via the input/output buffer IOB. Moreover, in the read operation,the read data from the memory cell is outputted to the input/output dataI/O0 to I/O15 through the input/output buffer IOB after it is sensed andamplified with the Y-switch/sense amplifier YS/SA.

[0046] In this case, the erase/write, read and moreover test mode aredetermined with the command user interface CUI based on the chip enablesignal/CE, output enable signal/OE, write enable signal/WE, writeprotect signal/WP and reset/power-down signal/RP, the sequence of eachmode is generated with the write state machine WSM based on thisdetermined mode and execution of erase/write mode, read mode and testmode is controlled based on this sequence.

[0047] Moreover, although explained later in detail, in thesemiconductor chip 2 of flash memory, the pad of the input/output dataI/O2 of the usual operation mode is used-in common with the input/outputserial data TIO, the pad of the write enable signal/WE with the burn-inreference clock signal TCK and the pad of the output enable signal/OEwith the mode set signal TMS in the wafer level burn-in mode. Therefore,only the pad of the burn-in enable signal TBE is provided exclusively.In addition, the power supply voltage VCC, reference voltage VSS arealso used in common with the pad of the usual operation mode.

[0048]FIG. 13 shows a further detail structure of the memory array MA ofFIG. 2. The memory array MA is divided into four banks BANK1 to BANK4.These banks BANK1 to BANK4 are structured to enable the read operationof the other bank, for example, of the bank BANK2 in parallel with thewrite (programming) operation of one bank, for example, the bank BANK1.

[0049] The bank BANK1 includes the flash fuse area FEA, OTP area OTPA,usual memory cell area NMR1 and Y-switch/sense amplifier YS/SA1. Thebank BANK2 includes the usual memory cell area NMR2, Y-switch/senseamplifier YS/SA2 and x-redundant memory cell area XRA1. The bank BANK3includes the usual memory cell area NMR3, Y-switch/sense amplifierYS/SA3 and X-redundant memory cell area XRA2. The bank BANK4 includesthe usual memory cell area NMR4 and Y-switch/sense amplifier YS/SA4.

[0050] The X-redundant memory cell area XRA1 may be used, for example,as the X-direction memory cells of the banks BANK1 and BANK2. Similarly,the X-redundant memory cell region XRA2 may be used, for example, as theX-direction spare memory cells of the banks BANK3 and BANK4. Here, theX-direction is assumed as the word line direction and the X-redundantmemory cell areas XRA1, XRA2 are formed for repair in unit of the wordline.

[0051] As can be understood from FIG. 13, the Y-redundant memory cellarea YRA and lock bit area LBA are provided respectively, in the Ydirection of each bank, with division into two areas of the Y-redundantmemory cell area/lock bit area YRA1/LBA1 and the Y-redundant memory cellarea/lock bit area YRA2/LBA2. The Y-redundant memory cell areas YRA1 andYRA2 are structured for repair in unit of the data line.

[0052] As explained with reference to FIG. 2, the flash fuse area FFAand OTP area OTPA may be selected respectively with the selection signalS1 (FLASH fuse Select) and S2 (OPT Select) from the command userinterface CUI. The X-redundant memory cell area XRA1 and X-redundantmemory cell area XRA2 are respectively selected with the selectionsignals S4-1 (Spare X-1 Select) and S4-2 (Spare X-2 Select) from thecommand user interface CUI. The Y-redundant memory cell areas YRA1 andYRA2 are respectively selected with the selection signals S5-1 (SpareYupper Select) and S5-2 (Spare Ylower Select) from the command userinterface CUI and the lock bit areas LBA1 and LBA2 are respectivelyselected with the selection signals S3-1 (Lock bit Select) and S3-2(Lock bit Select) from the command user interface CUI. Namely, for theareas FFA, OPTA, XRA1, XRA2, YRA1, YRA2, LBA1 and LBA2, the erase ofmemory cells, write and read processes are enabled within these areaswith the selection signals from the command user interface CUI.

[0053]FIG. 14 shows a relationship among the erase operation, writeoperation and read operation for the usual memory area (NMR), redundantmemory area (XRA, YRA), OTP area (OTPA) and flash fuse area (FFA).

[0054] In the usual memory area (NMR), the erase operation, writeoperation and read operation are all enabled.

[0055] The redundant area (XRA, YRA) are considered as the usual memorycell after implementation of repair of the defective memory cell and theerase operation, write operation and read operation are all enabled inthis area. However, before the repair of the defective memory cell, theerase, write and read operations are enabled in the redundant area (XRA,YRA) under the condition that the predetermined command such as the testcommand is inputted to the command user interface CUI.

[0056] In the OTP area (OTPA), the erase operation under the usualcondition is disabled but such erase operation is enabled under thecondition that the predetermined command such as the test command isinputted to the command user interface CUI. In the OTP area (OTPA), thewrite operation is enabled only once under the condition that thespecial command is inputted to the command user interface CUI. Moreover,when the memory cells in the OTP area (OPTA) are erased, the writeoperation is enabled under the condition that the special command isinputted to the command user interface CUI. In addition, the readoperation from the OTP area (OTPA) is enabled under the condition thatthe special command is inputted to the command user interface CUI.

[0057] On the other hand, the erase, write and read operations for thememory cells in the flash fuse area (FFA) are disabled in the usualcondition. However, these operations for the memory cells in the flashfuse area (FFA) are enabled only under the condition that thepredetermined command such as the test command is inputted to thecommand user interface CUI.

[0058] As explained above, the redundant area (XRA, YRA) OTP area (OTPA)and flash fuse area (FFA) may be used as explained later as thehistorical data storing area of burn-in process by providing thereto acertain kind of limitation for access.

[0059] Next, referring to FIG. 15, a layout of an example of thesemiconductor chip of flash memory will be explained based on FIG. 3.FIG. 3 is a layout diagram showing the semiconductor chip of flashmemory. FIG. 15 is an explanatory diagram showing a relationship betweenimplementation of the burn-in test to the memory cell area and storingarea of the burn-in test result.

[0060] In FIG. 3, the memory array MA of semiconductor chip 2 of flashmemory is divided into two sections of right and left sections and inthe right and left sections, respective sections are further dividedsandwiching the Y-switch/sense amplifier YS/SA. Between the memoryarrays MA divided into the right and left sides, a boost circuit BC isarranged and a predecoder PD is allocated at the upper side thereof.Moreover, at the upper side of the divided memory arrays MA, anX-decoder XD is allocated and at the upper side of the Y-switch/senseamplifier YS/YA, a Y-decoder YD is allocated. Moreover, at the upperside of the X-decoder XD and Y-decoder YD, the circuits such asX-address buffer XAB, Y-address buffer YAB, logic circuit LC, pumpcircuit PC, distributor DT, read-only memory ROM and static randomaccess memory SRAM or the like are allocated. In the logic circuit LC,the circuits such as command user interface CUI, write state machine WSMand data handler DH or the like are included. Moreover, in the left sideof the memory array MA, a fuse controller FC is allocated.

[0061] In addition, moreover, the pads for the control signals such asexternally inputted address signals A0 to A20, chip enable signal/CE,output enable signal/OE, write enable signal/WE, write protectsignal/WP, reset/power-down signal/RP and ready/busy signal RDY//BUSY,input/output data I/O0 to I/O15, power supply voltage VCC and referencevoltage VSS are allocated in the right and left peripheral areas of thesemiconductor chip 2 of the flash memory.

[0062] Particularly, in this embodiment, as shown in FIG. 2, the OTP(One Time Programmable) area OTPA, flash fuse area FFA and lock bit areaLBA are provided, in addition to the memory cell area NMR for writing aninput information of usual operation, within the memory array MA and thehistorical data of the electrical characteristic test can be writteninto these areas. The OPT area OPTA allows the programming only once andis provided as the area for mainly writing the intrinsic informationsuch as the manufacturing information of makers. The flash fuse area FFAis provided as the area for writing the redundant address/enableinformation for redundant repair by changing over the defective bits ofusual area for storing an input information of the usual operation intothe redundant repair bit. The lock bit area LBA is used to write thesetting information to prohibit the erase/write operations in unitblock. Among these areas, the OTP area OTPA and lock bit area LBA areprovided to conduct the burn-in test like the usual area during theburn-in operation, while the flash fuse area FFA is provided as the areawhere the burn-in test is not carried out.

[0063]FIG. 15 shows a relationship between implementation of the burn-intest for the usual memory area (NMR), redundant memory area (XRA, YRA),OTP area (OTPA) and flash fuse area (FFA) and the storing area of theburn-in test as the historical data of the electrical characteristictest.

[0064] In the usual memory area (NMR), OTP area (OTPA) the burn-in testis executed. In the redundant memory area (XRA, YRA), the burn-in testis conducted only for the memory cells used for repair after thedefective memory cells are repaired, but before the defective memorycells are repaired, the burn-in test is conducted for all memory cells.The burn-in test is not conducted to the flash fuse area (FFA) but theburn-in test can also be implemented under the condition that thepredetermined command such as the test command is inputted to thecommand user interface CUI.

[0065] The burn-in test result can be stored for all areas of the usualmemory area (NMR), redundant memory area (XRA, YRA), OTP area (OTPA) andflash fuse area (FFA). However, as is explained in regard to FIG. 15, itis desired that the historical data stored in respective areas such asthe usual memory area (NMR), redundant memory area (XRA, YRA) and OTParea (OTPA) are saved to the external apparatus such as a tester beforethe next burn-in test and other testing. When the burn-in test is notimplemented for the flash fuse area (FFA), it is not required to savethe historical data to be stored in the area.

[0066] Next, referring to FIG. 5 and FIG. 6, an example of the method ofmanufacturing MCP up to the assembling process from the wafer process,in which the semiconductor chip of flash memory and semiconductor chipof SRAM are mounted, will be explained based on FIG. 4. FIG. 4 is aflowchart showing the method of manufacturing MCP up to the assemblingprocess from the wafer process. FIG. 5 is a plan view showing thesemiconductor wafer condition and FIG. 6 is a plan view showing thesemiconductor chip condition.

[0067] First, in regard to the semiconductor chip 2 of flash memory, thewafer processes such as oxidation/diffusion/implantation of impurities,formation of wiring patterns, formation of insulation layers andformation of wiring layers are repeatedly conducted to form thepredetermined integrated circuit in the pre-process of the semiconductorwafer (step S101), thereafter the wafer level burn-in is conducted inthis semiconductor wafer condition (step S102), the semiconductor chip 2which will generate a fault in future is identified and the repair isexecuted, as explained later, in the repair process for suchsemiconductor chip 2. The wafer level burn-in test result is writteninto the semiconductor chip 2 of flash memory. Details of this waferlevel burn-in test will be explained later.

[0068] Thereafter, the wafer level burn-in test result is read toconduct the probe test (1) for the semiconductor chip of good product(step S103). This probe test (1) includes a function test to checkwhether the predetermined functions are attained or not by testing thememory function using the predetermined test pattern with theerase/write and read operations, for example, for the flash memory, theDC test such as the open/short inspection between the input and outputpads, leak current inspection and measurement of power supply currentand the AC test such as testing of the AC timing of the memory control.The result of this probe test (1) is written into the semiconductor chip2 of flash memory.

[0069] For the semiconductor chip 2 of defective product, a defectivebit is found by reading the result of probe test (1) and then analyzingthe test result and the repair is conducted by executing the redundantrepair process to this defective bit with the redundant repair circuit(step S104). In this repair process, the repair is also conducted in thesame manner for the semiconductor chip 2 which as been identified as thedefective chip in the burn-in test.

[0070] Moreover, it is confirmed that the defective bit is converted tothe bit for redundant repair with the redundant repair process byconducting again the probe test (2) of semiconductor chip 2 after therepair (step S105). The result of this probe test (2) is written intothe semiconductor chip 2 of the flash memory. Thereby, in regard to thesemiconductor chip 2 of flash memory, the pre-process in the stage ofsemiconductor wafer is completed, and thereby the semiconductor wafermounting a plurality of semiconductor chips 2 of flash memory havingcompleted the burn-in test can be generated.

[0071] In the same manner, also in regard to the semiconductor chip 3 ofSRAM, the semiconductor wafer mounting a plurality of semiconductorchips 3 of SRAM having completed the burn-in test can be generated byconducting, in the pre-process of the semiconductor wafer, the waferlevel burn-in (step S107), probe test (1) (step S108), repair (stepS109) and probe test (2) (step S110) after forming the predeterminedintegrated circuit by repeating the wafer processes.

[0072] Subsequently, the results of the probe tests (1), (2) are readand the MCP is assembled using the semiconductor chip 2 of flash memoryof good product and the semiconductor chip 3 of SRAM (step S111) First,as explained above, the semiconductor wafer of the flash memory andsemiconductor wafer of SRAM having completed the pre-process ofsemiconductor wafer are cut to separate each semiconductor chip asexplained above and thereby the semiconductor chip 2 of flash memory andsemiconductor chip 3 of SRAM isolated for each semiconductor chip areprepared.

[0073] For example, as an example, the flat structure is attained asshown in FIG. 5 in the condition of semiconductor wafer 11 or as shownin FIG. 6 in the condition of the cut-out semiconductor chips 2, 3.However, in FIG. 5 and FIG. 6, the number of semiconductor chips 2, 3mounted on the semiconductor wafer 11 and the number of pads provided inthe semiconductor chips 2, 3 are set to the values less than the actualvalues. For example, the semiconductor chips 2, 3 are set to 540 as anexample, while the pads to 50 as an example. In these semiconductorchips 2, 3, the pads are allocated in the two sides of the peripheralarea, but it is of course possible to introduce various changes ormodifications, for example, the semiconductor chips are allocated in theperipheral four sides or along the center line.

[0074] Thereafter, the die-bonding for mounting the semiconductor chip 2of flash memory and semiconductor chip 3 of SRAM on the substrate 1,wire bonding for connecting the pads of these semiconductor chips 2, 3and the pad on the substrate 1 with a wire 4, resin mold for molding thesemiconductor chips 2, 3 and wire 4 with resin 6 to protect theseelements and lead formation to form an external lead and conduct thesurface process are executed. Thereby, the assembling process of MCP ofthe package structure is completed to provide the structure ofcross-section as shown in FIG. 1 explained above.

[0075] Moreover, the operation test of MCP having completed theassembling process is conducted (step S112). In this operation test,like the probe test, for example, of the semiconductor chips 2, 3, thefunction test for confirming whether the predetermined function can beattained or not by testing the memory function using the predeterminedtest pattern with the erase/write and read operation for the flashmemory and SRAM, the DC test such as open/short inspection among theinput/output pads, leak current inspection and measurement of powersupply current and the AC test for testing the AC timing of the memorycontrol of flash memory and SRAM are conducted.

[0076] Finally, as a result of operation test of MCP, the historicaldata of MCP operation test and the historical data of wafer levelburn-in and probe test of the semiconductor chip 3 of SRAM are writtento the semiconductor chip 2 of flash memory only in the MCP of goodproducts (step S113). The historical data of the wafer level burn-in andprobe test of the semiconductor chip 2 of flash memory is alreadywritten into the semiconductor chip 2 of the flash memory. Only the MCPsto which this historical data is written are delivered as the goodproducts. Depending on the result of this operation test of MCP, MCP isassembled by combining the flash memory having completed the burn-intest and the semiconductor chips 2, 3 of SRAM, the burn-in process inthe assembling process is no longer required and the yield of operationtest of the assembled product can be raised.

[0077] Next, with reference to FIG. 7, an example of the test system torealize the wafer level burn-in of the semiconductor chip of flashmemory will be explained. FIG. 7 is a block diagram showing the testsystem to realize the wafer level burn-in.

[0078] The test system is composed of a semiconductor wafer 11 mountinga plurality of semiconductor chips 2 of flash memory as explained above,a burn-in board 22 to conduct the burn-in by placing the probe 21 incontact with the pad of each semiconductor chip 2 of this semiconductorwafer 11 and a testing apparatus 23 for inputting and outputting varioussignals such as a burn-in reference signal for burn-in, a burn-in enablesignal, a mode set signal and an input/output serial data. The burn-inboard 22 is also provided with a parallel/serial converting circuit 24to output the parallel data of input/output data outputted from eachsemiconductor chip 2 to the testing apparatus 23 through conversion tothe serial dada. The test system to realize the wafer level burn-in ofthe semiconductor chip 1 of SRAM is also formed in the similarstructure.

[0079] In this testing system, the burn-in reference clock signal,burn-in enable signal and mode set signal generated from the testingapparatus 23 are supplied to each semiconductor chip 2 of thesemiconductor wafer 11 via each buffer of the burn-in board 22.Moreover, the input/output data outputted from each semiconductor chip 2is converted to the serial data from the parallel data in theparallel/serial converting circuit 24 in the burn-in board 22 and isthen fetched with the testing apparatus 23. The testing apparatus 23 andthe parallel/serial converting circuit 24 of burn-in board 22 arecontrolled with the parallel/serial control signal.

[0080] Next, an example of the wafer level burn-in of the semiconductorchip of flash memory will be explained in detail with reference to FIG.8. FIG. 8 is the flowchart showing the wafer level burn-in of the flashmemory.

[0081] The wafer level burn-in is a testing method for testing at a timethe semiconductor chips 2 of all flash memories under the condition ofsemiconductor wafer 11 completed in the preceding process.

[0082] (1) In the wafer level burn-in process, the probe 21 of theburn-in board 22 is placed in contact with the pad of the semiconductorchip 2 of each flash memory of the semiconductor wafer 11 and the powersupply (VCC/VSS) is supplied at a time to each semiconductor chip 2(step S201).

[0083] (2) Subsequently, the contact check (open/short) is executed forthe input/output pad of each semiconductor chip 2 (step S202) and thehistorical data of contact check is written into the conductivesemiconductor chip 2 (step S203). In this case, the historical data isnot written into the non-conductive semiconductor chip 2 in the contactfailure condition and this semiconductor chip 2 is processed as thedefective product.

[0084] In this case, when the area for writing the historical data tothe rewrite areas for erase/write operations such as the OTP area OTPAand lock bit area LBA is set within the memory array MA explained above,the information is read, for example, with the testing apparatus totemporarily save the historical data before starting the burn-in testand the data obtained by combining the historical data before therewrite test and the historical data after this rewrite test isrewritten into the semiconductor chip 2.

[0085] Moreover, if the area for writing the historical data, forexample, is different from the rewrite area for the erase/writeoperation like the flash fuse area FFA, the erase/write mode isimplemented in direct to the rewrite area for erase/write operation andthe historical data after this test can be written into thesemiconductor chip 2.

[0086] (3) Next, the erase/write mode (rewrite test) is implanted as theburn-in test to the memory array MA of each semiconductor chip 2 (stepS204) and the historical data (pass/fail) of the burn-in result of thiserase/write mode is written into the semiconductor chip 2 like thehistorical data of the contact check (step S205).

[0087] (4) Subsequently, the read mode similar to that for the usualmemory is implemented to the memory array MA of each semiconductor chip2 (step S206) as the burn-in and the historical data (pass/fail) of theburn-in result of this read mode is written into the semiconductor chip2 just like the historical data explained above (step S207). The waferlevel burn-in process is thereby finished.

[0088] (5) In the probe test process following the wafer level burn-inprocess, the historical data written in the wafer level burn-in processis read first (step S208) to determine whether the relevant chip is goodproduct (pass) or defective product (fail) (step S209). The probe testis continuously executed only to the good semiconductor chip 2 (stepS210). The historical data of this probe test is also written to thesemiconductor chip 2. Here, the repair process is executed to thedefective semiconductor chip 2 (step S211).

[0089] As explained above, the testing time can be shortened by writingthe historical data of the electrical characteristic test of the contactcheck, erase/write mode and read mode because it is enough, for example,when the wafer level burn-in test is shifted to the probe test, tocontinue only the test of the semiconductor chip 2 as the good productby reading the historical data of the preceding test at the time ofstarting the next test.

[0090] Next, an example of the wafer level burn-in mode will beexplained in detail with reference to FIG. 9 to FIG. 12. FIG. 9 is ablock diagram showing the circuit including the wafer level burn-infunction of flash memory. FIG. 10 is a timing chart showing the waferlevel burn-in mode. FIG. 11 is an explanatory diagram showing a dataformat of the wafer level burn-in mode. FIG. 12 is an explanatorydiagram showing a setup command of the wafer level burn-in mode.

[0091] As shown in FIG. 9, the circuit including the wafer level burn-infunction of flash memory is formed of the command user interface CUIincluded in the logic circuit LC, write state machine WSM and datahandler DH or the like and these area connected with each other via theaddress bus R2ADDR, data bus R2DATA and control signal bus IOD. Thewafer level burn-in mode is implemented using the input/output signalsfor the semiconductor chip 2 of flash memory such as input/output serialdata TIO, burn-in reference clock signal TCK, burn-in enable signal TBE,mode set signal TMS, power supply voltage VCC and reference voltage VSS.

[0092] For example, the pad of the input/output serial data TIO is usedin common with the input/output data of usual operation mode I/O2, thepad of the burn-in reference clock signal TCK with the write enablesignal/WE, the pad of the mode set signal TMS with the output enablesignal/OE and moreover only the pad of the burn-in enable signal TBE isprovided exclusively. The pads of the power supply voltage VCC andreference voltage VSS are identical to that of the usual operation mode.Each signal of these wafer level modes has the function explained below.

[0093] (1) The burn-in enable signal TBE is controlled with an inputfrom the exclusive pin for the wafer level burn-in or issuance ofevaluation command (WLBI-MODE-SET) from the test mode. When theevaluation command is issued for entry to the wafer level burn-in, thewafer level burn-in is completed by issuing the WLBI-END command andthereby the burn-in mode is returned to the usual test mode. Forexample, the wafer level burn-in mode does not start when TBE is in the“H” level but starts when TBE is in the “L” level. It is because aselector opens to accept the wafer level burn-in command when the signalPAD-TBE enters the command user interface CUI.

[0094] (2) The mode set signal TMS changes while the burn-in referenceclock signal TCK is in the “H” level (TCK=“H”). When the burn-in enablesignal TBE is in the “L” level, the mode set signal TMS becomes “H” toswitch the mode. Namely, the signal TMS is the mode signal to become thecommand input condition when it is in the “H” level and to execute theoperation when it is in the “L” level (TBE=“L” and AND). However, if allcommands are not inputted (60 times), the wafer level burn-in is notexecuted even in the “L” condition.

[0095] (3) The burn-in reference clock signal TCK is the referencesignal for the wafer level burn-in and sequentially fetches (2 bits) theinput condition of the input/output serial data TIO while the TCK risesto the command register of the command user interface CUI when burn-inenable signal TBE is in the “L” (TBE=“L”) level and the mode set signalTMS is in the “H” level (TMS=“H”).

[0096] (4) The input/output serial data TIO switches the input andoutput with the mode set signal TMS (input: #1 to #60, output: #A to#D).

[0097] The command user interface CUI comprises the circuit blocksWLBI-ENTRY, WLBI-RST and OUTPUT-CONT or the like to receive as theinputs signals the burn-in reference clock signal TCK, burn-in enablesignal TBE (PAD-TBE) and mode set signal TMS from the external circuitsand the FUSE-latch signal and COM-TBE signal from the internal circuitand output the C2BTMS signal, WLBI-END signal, WLBI-RST signal andFUSE-OSEL signal or the like. Moreover, this command user interface CUIalso receives as the input signals the data of the address bus R2ADDR,data bus R2DATA and control signal bus IOD.

[0098] The write state machine WSM is connected to the address busR2ADDR, data bus R2DATA and control signal bus IOD to receive as theinput signals the data of the address bus R2ADD and data bus R2DATA tooutput the data to the control signal bus IOD. This write state machineWSM is connected to the memory array MA from the multiplexer MPexplained above.

[0099] The data handler DH includes the circuit block WLBI-REG and isconnected to the address bus R2ADDR, data bus R2DATA and the controlsignal bus IOD to receive as the input signals the data of the addressbus R2ADDR, data bus R2DATA and control signal bus TOD. This datahandler DH is also connected to the multiplexer MP as explained above.Each circuit block within these command user interface CUI and datahandler DH has the function explained below.

[0100] (1) The circuit block WLBI-ENTRY sets the wafer level burn-inmode. This circuit fetches the 12-bit serial data (setup command)inputted as the input/output serial data TIO and the subsequent 48-bitserial data (trimming setup data) to reflect these signals to theregister after the serial/parallel conversion. The command userinterface CUI recognizes the mode by reading the register immediatelyafter it is driven.

[0101] (2) The circuit block WLBI-RST generates a reset signal for waferlevel burn-in enable (TBE=“L”) After the burn-in enable signal TBEfalls, this reset signal becomes the “H” pulse signal during the perioduntil the next burn-in reference clock signal TCK rises from fall of theburn-in enable signal TBE. This signal WLBI-RST is ORed with the masterreset in the block rsRESET.

[0102] (3) The circuit block OUTPUT-CONT continuously inputs the clocksT1 and T2 because the write enable signal/WE becomes the burn-inreference clock signal TCK during the wafer level burn-in. In this case,this circuit block controls the clock input as many times as required,internally controls the command data and generates the required controlsignal during the wafer level burn-in.

[0103] (4) The circuit block WLBI-REG executes the control to output inserial the wafer level burn-in condition from the pad of theinput/output serial data TIO. During the read operation (data output),the usual memory data is outputted from the pad of input/output serialdata TIO through the parallel/serial conversion, while during theerase/program mode, the resister data is outputted and during the othercases, the data of circuit WLBI-REG is outputted.

[0104] In the flash memory including the wafer level burn-in function asexplained above, a command of the CHIP-ERASE mode is generated withinthe command user interface CUI is generated for the erase mode, while acommand of the Write Buffer to Flash mode for the program mode andthereby the signal Busy is generated in the write state machine WSM forthe driving purpose. Thereby, the write state machine WSM sequentiallychecks the 12 bits of the command register, establishes the necessarysetting and then executes the erase program sequence.

[0105] The data handler DH is a latch circuit for outputting thecondition of the wafer level burn-in as the input/output serial data TIOand outputs, by receiving the condition of the command register of thecommand user interface CUI, the status set in the data handler DH duringthe contact check, or the read status during the read mode, or the erasestatus during the erase mode, or the program status during the programmode, or no data therefrom only during the read data output but anoutput data from the memory cell as the input/output serial data TIO.This input/output serial data TIO is outputted when the burn-inreference clock signal TCK falls while the mode set signal TMS is in the“L” level and the burn-in enable signal TBE is in the “L” level.

[0106] For example, as the setting of the write data during the programmode, the data of 256 bits are set to the all “0” to write the 2048 bits(data transfer to 256 bits×16 bit lines). Of the 4096 bits of the dataline, 2048 bits are written in every other bit and the data in which “0”and “1” are inverted can be written to the adjacent word lines bysetting the address transition to the next word line+1 bit line. Duringthe erase mode, this ease mode is executed by setting the verify data(expected value) to all “1” for the simultaneous erase of block. Onlyduring the write mode of historical data, the desired data of 4 bits canbe set to bit 3 to 0.

[0107] In regard to determination of with/without verify, when thedefective bit is repaired, the usual sequence is completed in the resultof with verify, but if the program/erase is executed under the conditionthe defective bits are left, the verify of the defective bit cannot passthe check and the test is completed in this stage. Therefore, thesetting of with/without verify must be conducted to apply the stress toall bits.

[0108] Moreover, in regard to the scanning method (skip & domino·programsystem), it is effective only in the program mode and the bit lines areusually selected with shift in unit of 200 ns when there is no defectivebit to realize the write mode of 2048 bits. This write operation isbased on the balance between the write current of memory cell and thecurrent generated in the internal voltage generating circuit. Therefore,since 10 bits are selected simultaneously during the write operation ofone bit, if a fault of one bit exists, a current is leaked therefrom ina certain case. Accordingly, the next bit is selected with shift in unitof 2 μs which is the time required for write mode.

[0109] As shown in FIG. 10, in the wafer level burn-in mode, after theburn-in enable signal TBE is shifted to “L” from “H”, the mode set canbe executed by shifting the mode set signal TMS to “H” from “L” andwhile the mode set signal TMS is in the “H” level, the rewrite data canbe inputted to the memory cell as the input/output serial data TIO insynchronization with the burn-in reference clock signal TCK. Moreover,execution of the wafer level burn-in mode and output of status can beexecuted by shifting the mode set signal TMS to “L” from “H” while theburn-in enable signal TBE is kept at “L” level and while the mode setsignal TMS is in the “L” level, the read data and status of the memorycell can be outputted as the input/output serial data TIO insynchronization with the burn-in reference clock signal TCK.

[0110] As shown in FIG. 11, the wafer level burn-in mode can be set byserially inputting the information of 60 bits consisting of the setupcommand formed of 12 bits (b11 to b0) and sequential trimming set dataof 48 bits (F47 to F0) as the input/output serial data TIO. In thiscase, the input data is inputted in synchronization wit the burn-inreference clock signal TCK.

[0111] As shown in FIG. 12, the bit 11 of the wafer level burn-in (WLBI)mode setup command indicates the wafer level burn-in enable, bits 10, 9indicate selection of the wafer level burn-in operation, bit 8 indicatesthe historical data write option, bit 7 indicates the wafer levelburn-in trimming, bit 6 indicates selection of wafer level burn-in area,bits 5, 4 indicate selection of memory operation (MF), bit 3, 2 indicateselection of memory pattern (MP), bit 1 indicates with/without verifyand bit 0 indicates scanning method (during program mode), respectively.

[0112] (1) In the wafer level burn-in enable of bit 11, the bit “0”designates the normal operation and bit “1” designates the wafer levelburn-in operation.

[0113] (2) In the selection of wafer level burn-in operation with thebits 10, 9, the bits “0, 0” designate the operation to write thehistorical data of wafer level burn-in and the bits 7 to 4 designate thearea set and the bits 3 to 0 designates the data set. Moreover, the bits“0, 1” designate the end of wafer level burn-in and the bits 8, 6 to 0are neglected. Moreover, the bits “1, 0” designate the wafer levelburn-in operation and the bits 7 to 0 are set freely.

[0114] (3) In the historical data write option of bit 8, the bit “0”designates the over-write operation and the bit “1” designatescombination of erase and write operations.

[0115] (4) In the wafer level burn-in trimming of bit 7, the bit “0”designates use of the flash fuse data as the trimming data and the bit“1” designates use of the 48-bit load data as the trimming data. In thiscase, the trimming set data of 48 bits is inputted following the modesetup command. In the case of no trimming, the dummy of 48 bits isinputted. For example, during the wafer level burn-in operation, the bitis set to “1”.

[0116] (5) In the selection of wafer level burn-in area of bit 6, thebit “0” selects the usual operation area (32M) and OTP area, while thebit “1” selects the all areas, namely the usual operation area,redundant repair X, Y area and OTP area. For example, for the waferlevel burn-in operation, the bit is set to “1”. These redundant repairX, Y areas are particular X area and Y area for repairing the defectivebits of the usual operation area, while the OTP area is the particulararea enabling only once the data write operation.

[0117] (6) In the selection of memory operation (MF) of bits 5, 4 andselection of memory pattern (MP) of memory pattern of bits 3, 2, thebits “0, 0, 0 or 1, 0 or 1” designate the open check, the bits “0, 1, 0,0 or 1” designate the read data output, the bits “0, 1, 1, 0 or 1”designate the read status output, the bits “1, 0, 0 or 1, 0 or 1”designate the erase, the bits “1, 1, 0, 0” designate the program all 0,the bits “1, 1, 0, 1” designate the program checker, the bits “1, 1, 1,0” designate the checker bar in which the program checker is inverted.For example, on the occasion of wafer level burn-in operation, the bitsare set to “0, 0, 0, 1” for the contact check, the bits are set to “1,0, 0, 1” and “1, 1, 0, 1” for the erase/write mode and the bits are setto “0, 1, 0, 1” for the read mode, respectively.

[0118] (7) In the with/without verify of the bit 1, the bit “1”designates with verify, while the bit “0” designates without verify.Usually, if the target level will not probably be attained even with theretry, the bit is set to “1”. For example, in the case of the waferlevel burn-in operation, the bit is set to “1”.

[0119] (8) In the scanning method (during the program mode) with the bit0, the bit “0” designates the scanning in the delay of 200 ns with theskip (S) & domino (d) and the bit “1” designates the scanning in thedelay of 2 pm with the skip & domino. This skip & domino means thescanning method in which the scanning is conducted while the desirednumber of bits are skipped. For example, the bit is set to “1” for thewafer level burn-in operation.

[0120] As explained above, the wafer level burn-in test can be executedby setting the wafer level burn-in mode in the flash memory includingthe wafer level burn-in function.

[0121] Therefore, according to the profile of this embodiment, since itis enough to continue the test of only the semiconductor chip 2 of thegood product after reading the historical data of wafer level burn-in atthe time of next test such as the probe test by writing and storing thehistorical data of wafer level burn-in to the area where the informationbefore the wafer level burn-in of the semiconductor chip 2 of flashmemory is not erased, the time required by the next test can beshortened and thereby the screening cost can also be lowered. Moreover,even in the case where the historical data is written and stored to thearea where the information is eased in the wafer level burn-in test, thetime required by the next test can be shortened and the screening costcan also be lowered in the same manner by temporarily saving the databefore the burn-in test to the testing apparatus 23 and then writingback the combined data to the semiconductor chip 2 after the burn-intest.

[0122] Moreover, since only the semiconductor chip 2 of good product canbe sent to the assembling process after checking the historical data inthe assembling process by storing the historical data of the wafer levelburn-in test and probe test in the semiconductor chip 2 of flash memory,sending of a defective product to the assembling process can beprevented easily and thereby the reliability of semiconductor chip 2 canthen be improved.

[0123] Moreover, even in the MCP in which the semiconductor chip 2 offlash memory and semiconductor chip 3 of SRAM are sealed, the historicaldata of the wafer level burn-in test, probe test and operation test ofMCP in the semiconductor chip 2 of flash memory stored in thesemiconductor chip 2 of flash memory and the semiconductor chip 3 ofSRAM can be checked easily when a fault is generated in the customerside, a fault analysis of a product can be conducted easily.

[0124] The present invention has been practically explained based on thepreferred embodiment thereof but the present invention is not restrictedto the preferred embodiment and may be of course changed and modifiedwithin the scope of the claims thereof.

[0125] For example, in the preferred embodiment, an example of MCPmounting two semiconductor chips of flash memory and SRAM has beenexplained but it is also possible to introduce various changes andmodifications for the structure of assembling parts such as thecombination of a non-volatile flash memory and a volatile memory such asRAM, DRAM or SDRAM and a combination of non-volatile memories andcombination of three or more memories. Therefore, the present inventioncan be widely adapted to almost all kinds of semiconductor devices inwhich at least non-volatile flash memory is loaded.

[0126] Moreover, it is enough for the semiconductor chip ofsemiconductor wafer to have the structure including the non-volatilememory area for storing the historical data of the wafer level burn-intest.

[0127] The effects of the typical inventions of the present inventiondisclosed in this specification are as follows.

[0128] (1) Since it is enough for the next electrical characteristictest such as the probe test to additionally continue the test of onlythe semiconductor chip of a good product in the historical informationof the preceding electrical characteristic test by writing and storing,to the semiconductor chip of non-volatile memory, the historicalinformation of the electrical characteristic test such as the waferlevel burn-in test. Thereby, the test time of the electricalcharacteristic test can be shortened and accordingly the screening costof the semiconductor chip can also be lowered.

[0129] (2) Since only the semiconductor chip having the historicalinformation proving the good product can be sent in the assemblingprocess by storing the historical information of the electricalcharacteristic test such as the wafer level burn-in test and probe testinto the semiconductor chip of non-volatile memory, leak of defectiveproduct into the assembling process can be prevented easily and therebythe reliability of the semiconductor chip and the semiconductor deviceloading the same semiconductor chip can be so far improved.

[0130] (3) In a semiconductor device mounting only a semiconductor chipof a non-volatile memory or mounting a semiconductor chip ofnon-volatile memory and a semiconductor chip of volatile memory, if afault in the customer side is generated after delivery to the customer,the historical information stored in the semiconductor chip ofnon-volatile memory can be checked easily. Therefore, the cause of afault generated in the semiconductor device can be analyzed easily.

[0131] (4) According to the items (1) to (3), in the case where asemiconductor chip of the non-volatile memory is delivered as a productor in the case where a semiconductor device mounting only thesemiconductor chip of non-volatile memory or the semiconductor chip ofnon-volatile memory and the semiconductor chip of volatile memory isdelivered as a product, cost can be lowered and reliability of theproduct can be improved through reduction of the screening time.

What is claimed is:
 1. A semiconductor wafer comprising: a plurality ofsemiconductor chips each of which also includes a non-volatile memoryarray, wherein said plurality of semiconductor chips each comprises: afirst memory area for storing input information of usual operation; anda second memory area for storing historical information of an electriccharacteristic test of said first memory area.
 2. A semiconductor waferaccording to claim 1, wherein said electrical characteristic test is awafer level burn-in test.
 3. A semiconductor wafer according to claim 2,wherein said second memory area is a flash fuse area of saidnon-volatile memory area.
 4. A semiconductor wafer according to claim 2,wherein said second memory area is an OTP area of said non-volatilememory area.
 5. A semiconductor wafer according to claim 2, wherein saidsecond memory area is a lock bit area of said non-volatile memory area.6. A semiconductor wafer according to claim 2, wherein said secondmemory area is a part of said first memory area of said non-volatilememory area.
 7. A semiconductor chip including a non-volatile memoryarray, comprising: a first memory area for storing input information ofusual operation; and a second memory area for storing historicalinformation of an electrical characteristic test of said first memoryarea.
 8. A semiconductor chip according to claim 7, wherein saidelectrical characteristic test is a wafer level burn-in test.
 9. Asemiconductor device mounting a semiconductor chip including anon-volatile memory array, said non-volatile memory array comprising: afirst memory area for storing input information of usual operation; anda second memory area for storing historical information of an electricalcharacteristic test of said first memory area.
 10. A semiconductordevice according to claim 9, wherein said electrical characteristic testis a wafer level burn-in test.
 11. A semiconductor device comprising: afirst semiconductor chip including a non-volatile memory arraycomprising: a first memory area for storing input information of usualoperation, and a second memory area for storing historical informationof an electrical characteristic test of said first memory area; and asecond semiconductor chip including a volatile memory array comprising athird memory area for storing input information of usual operation,wherein historical information of an electrical characteristic test ofsaid third memory area of said second semiconductor chip is stored intosaid second memory area of said first semiconductor chip.
 12. Asemiconductor device according to claim 11, wherein said electricalcharacteristic test is the wafer level burn-in test.
 13. A method ofmanufacturing a semiconductor device including a semiconductor chiphaving a non-volatile memory array cut out from a semiconductor wafer,the method comprising: conducting an electrical characteristic test of afirst memory area for storing input information of usual operation ofsaid semiconductor chip before cutting out said semiconductor chip fromsaid semiconductor wafer; and storing said historical information ofsaid electrical characteristic test to the second memory area of saidsemiconductor chip.
 14. A method of manufacturing a semiconductor deviceaccording to claim 13, wherein said electrical characteristic test is awafer level burn-in test.
 15. A method of manufacturing a semiconductordevice according to claim 14, wherein historical information of saidsecond memory area is temporarily saved, at the time of conducting thewafer level burn-in test, to a testing apparatus before starting saidwafer level burn-in test, and wherein this historical information iscombined, after the wafer level burn-in test, with the historicalinformation before the test and the combined historical information isthen stored in said second memory area.
 16. A method of manufacturing asemiconductor device including a first semiconductor chip having anonvolatile memory array cut out from the semiconductor wafer and asecond semiconductor chip having a volatile memory array, comprising thesteps of: conducting an electrical characteristic test of a first memoryarea for storing input information of usual operation of said firstsemiconductor chip before cutting out said semiconductor chip from saidsemiconductor wafer; storing historical information of an electricalcharacteristic test of said first memory area of said firstsemiconductor chip to the second memory area of said first semiconductorchip; conducting an electrical characteristic test of the third memoryarea for storing input information of usual operation of said secondsemiconductor chip before cutting out said semiconductor chip from saidsemiconductor wafer; and storing historical information of an electricalcharacteristic test of said third memory area of said secondsemiconductor chip to said second memory area of said firstsemiconductor chip.
 17. A method of manufacturing a semiconductor deviceaccording to claim 16, wherein said electrical characteristic test is awafer level burn-in test.
 18. A method of manufacturing a semiconductordevice according to claim 17, wherein the historical data of said secondmemory area of said first semiconductor chip is temporarily saved, atthe time of conducting the wafer level burn-in test, to a testingapparatus before starting said test, and wherein this historicalinformation is combined, after this test, with the historicalinformation before the test to store the combined historical informationto said second memory area of said first semiconductor chip.